1. Field of the Invention
The present invention relates to a delay circuit, a semiconductor control circuit, a display device, and an electronic device.
2. Description of the Related Art
Generally, when an inverter circuit is formed on an insulating substrate of a display device integral with a driving circuit, in a polysilicon process or an amorphous silicon process for TFTs (Thin Film Transistors), variations in transistor characteristics such as threshold voltage Vth, mobility μ and the like are larger than in a single-crystal process.
FIG. 1 is a diagram showing a buffer circuit (hereinafter referred to as a delay buffer circuit) formed by connecting typical CMOS (complementary metal-oxide semiconductor) inverter circuits in two stages to each other.
This circuit has advantages of a simple configuration (small area), a small leakage current (low power consumption) and the like.
It is known, however, that an amount of delay of an output OUT with respect to an input IN is varied depending on variations in characteristics (threshold voltage and mobility) of an N-channel transistor (hereinafter referred to as Nch Tr) or a P-channel transistor (hereinafter referred to as Pch Tr).
That is, the amount of delay is one of quantities that represent the characteristics of the transistor. The amount of delay is large when the characteristics of the transistor are poor. The amount of delay is small when the characteristics of the transistor are good.
A digital circuit can compare the amount of delay easily. Thus, when the amount of delay can be detected accurately, the characteristics of the transistor should be detected easily.
However, the amount of delay by the typical inverter formed by CMOS transistors greatly depends on both Nch Tr and Pch Tr, and is thus unpractical.
For example, FIG. 2 is a diagram showing a relation between an amount of delay of a delay buffer circuit fabricated by a polysilicon process and the characteristics of Nch Tr and Pch Tr.
Inverter circuits formed by merely single-channel transistors are taken up in a few non-patent and patent documents.
For example, there is a bootstrap type inverter circuit introduced in Hisashi Hara, “Fundamentals of MOS Integrated Circuit”, Kindai Kagaku Sha Co., Ltd., pp. 94-96 (hereinafter referred to as Non-Patent Document 1). FIG. 3 is a diagram showing the circuit described in Non-Patent Document 1.
The circuit of FIG. 3 includes three single-channel transistors (Pch Tr) Q11, Q12, and Q13 and a capacitor C11.
FIG. 4 is a diagram showing a bootstrap type inverter circuit using single-channel transistors (Pch Tr) introduced in Japanese Patent Laid-Open No. 2005-143068 (hereinafter referred to as Patent Document 1).
A transistor Qp21 has a source connected to a VDD power supply, and has a gate supplied with an input signal IN via a circuit input terminal 21. An output signal OUT is derived from the drain of the transistor Qp21 via a circuit output terminal 22.
A transistor Qp22 has a source connected to the drain of the transistor Qp21, and has a drain connected to a VSS power supply. A capacitance Cp21 is connected between the gate and the source of the transistor Qp22. The capacitance Cp21 forms a bootstrap circuit 23 together with the transistor Qp22.
A transistor Qp23 has a source connected to the gate of the transistor Qp22, and has a drain connected to the VSS power supply. The gate of the transistor Qp23 is supplied with a reference signal REF1. A point of connection between the source of the transistor Qp23 and the gate of the transistor Qp22 will be referred to as a node ND. A transistor Qp24 has a source connected to the VDD power supply, and has a drain connected to the node ND. The gate of the transistor Qp24 is supplied with a reference signal REF2.
FIG. 5 is a diagram showing the respective levels of and timing relation between the input signal IN, the reference signals REF1 and REF2, the potential of the node N, and the output signal OUT in the circuit of FIG. 4.
A period during which the reference signal REF1 is at a VSS level is referred to as a precharge period. A period during which the reference signal REF2 is at the VSS level is referred to as a reset period.
By providing these reset and precharge periods, it is possible to suppress a leakage current, make the amplitude of potential of the output signal OUT equal to the amplitude of potential of the input signal IN, and increase the number of stages.